As CMOS devices keep scaling down, the gate oxide thickness becomes thinner. This presents a great challenge to traditional capacitance measurement used to monitor dielectric thickness for process variation. For example, an increase of the gate leakage current occurs at a rate of about one decade per 1.5 angstroms. When the equivalent oxide thickness (“EOT”) is below fifteen angstroms, the traditional method of extracting the capacitance vs. voltage (“C-V”) characteristic of the oxide by low frequency measurements on a block MOS capacitor is rendered invalid because of the gate leakage.